The present invention is directed generally to semiconductor memory architectures of a type having a number of bit cells arranged in a row and column array. More particularly, the memory includes an additional column of bit cells that are used to produce a self-timed control signal that estimates the time for sampling accessed bit cells.
Semiconductor memory design today typically includes a plurality of memory cells arranged by rows and columns to form an array. Each row of memory cells connects to a word line that, when activated by the decoding of an address, accesses access the bit cells of that row. Word line activation causes the data of each bit cell of the row to be passed to a pair of bit lines of the column in which the bit cell is located. A sense amplifier is then enabled at the appropriate time to sample the voltage difference on the bit lines, and convey the sampled data to a data bus for some other output. Sampling the bit lines too early, i.e., before the differential true/complement voltages are fully developed can result in an incorrect reading of the bit lines. Sampling the bit lines later than really needed tends to slow down operation.
A number of technologies are used to implement such memory architectures. One such technology and architecture is the use of complementary MOS (CMOS) technologies to implement a static RAM (SRAM) memory architecture. Recent advances in this technology and architecture has resulted in memories that have high-speed, low power, and are easy to use (i.e., not refresh circuitry as in dynamic RAM constructions), providing significantly more storage, faster access, and lower price. However, efforts to squeeze more and faster circuitry onto a semiconductor chip has made the circuitry more vulnerable to manufacturing variations, power fluctuations, and operating environmental changes. For example, variations in the process used to produce the memory circuit, can cause the circuitry formed on one part of the semiconductor chip to have different operating characteristics from circuity on another part of that chip. This is particularly troublesome when generating the timing signals, such as the enable signal to tell the sense amplifiers when to sample their respective bit lines. Variations such as these can cause the sense amplifiers to sample bit lines too early, producing possible erroneous data.
One design approach taken to accommodate such variations has been the incorporate of self-timing circuitry to provide, for example, a signal that enables sampling of an accessed cell at the right time. Self-timing allows the generated timing to vary according to similar variations imposed upon the memory itself--whether process variations or variations resulting from operating conditions (e.g., temperature and/or power fluctuations). One such technique is the use of an inverter chain to delay an earlier signal to generate array control signals. This technique, however, has three major disadvantages. First, the delay variation can be enhanced by threshold and supply voltage variations in memory circuits designed for low voltage operation. Therefore, threshold voltage and internal supply voltage variations can cause more delay mismatches between inverter chains in the control section and memory array area Secondly, the bit cell structure often uses small sized transistors, usually a smaller size than minimum W of logic area, in an effort to obtain higher circuit density. These small W transistors are more vulnerable to process variations than typical devices in the inverter chain which magnifies delay mismatches. Lastly, inverter chain delays are dominated in both NMOS and PMOS variations while memory cell current is only a function of NMOS.
Accordingly, an approach that eliminate these disadvantages is needed.